(1) Field of the Invention
The present invention relates to a solid-state imaging device, a semiconductor integrated circuit, and a signal processing method, and to a technique that converts an analogue signal obtained through photoelectric conversion into a digital signal.
(2) Description of the Related Art
In recent years, with a significant increase in number of pixels in a solid-state imaging device, demands for a technique that reads signals at high speed from the solid-state imaging device have been growing.
With an early structure where an analogue signal obtained through photoelectric conversion in a pixel circuit is read and sent outside a solid-state imaging device and converted into a digital signal using an external Analog Digital (AD) converter, an improvement in reading speed is limited due to a floating capacitance and the like inside the solid-state imaging device.
As a countermeasure to the above problem, a technique is known which converts an analogue signal obtained in a pixel circuit into a digital signal within the solid-state imaging device to suppress adverse effects such as the floating capacitance, thereby attaining speeding up signal output (See, for example, Patent Reference 1: Japanese Unexamined Patent Application Publication No. 2005-323331).
FIG. 25 is a schematic view illustrating a structure of main parts of a solid-state imaging device disclosed by Patent Reference 1. This solid-state imaging device converts a signal voltage obtained from a pixel circuit 92 into a digital signal through integral-type AD conversion. An operation of the solid-state imaging device will be roughly described.
The pixel circuit 92 in an imaging unit 91 applies, to one of input terminals of a voltage comparing unit 93, a signal voltage obtained through photoelectric conversion. A comparative signal generation unit 95 generates, by using a digital analog (DA) converter, a ramp wave RAMP which increases in synchronization with a clock signal CK provided by a control unit 94, and applies the ramp wave RAMP to the other one of the input terminals of the voltage comparing unit 93.
A counter unit 96 starts counting the clock signals CK simultaneously with the start of an increase of the ramp wave RAMP. When a signal indicating that a level of the ramp wave RAMP matches the signal voltage applied by the pixel circuit 92 is provided, the counter unit 96 outputs a count value as a digital signal indicating the signal voltage applied by the pixel circuit 92.
However, in order to obtain a digital signal at high speed with the conventional techniques, it is required to determine the time when the level of the ramp wave RAMP matches the signal voltage applied by the pixel circuit 92 in a short amount of time. For that reason, it is necessary to sweep the ramp wave RAMP at high speed by using a high-speed (in other words, high-frequency) clock signal CK.
A clock signal CK of 410 MHz frequency needs to be employed in order to obtain 12-bit digital output within 10 μs, for example. Further, in order to obtain 14-bit digital output, a clock signal CK of 1.6 GHz frequency needs to be employed.
Since it entails a high degree of technical difficulty to implement a circuit which operates stably under such a high-speed clock, practical application of the solid-state imaging device that allows both a multi-bit digital output and a high-speed output is difficult with the conventional technique.